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REV. B
AD1837
–7–
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
A
AVDD
O
N
OUTL2
NC
OUTR1
NC
OUTL1
NC
PD
/
RST
CIN
CLATCH
DVDD
N
O
NC
OUTR3
NC
OUTL4
NC
OUTR4
AGND
DLRCLK
DBCLK
D
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
52
51
50
49
48
47
46
45
44
43
42
41
40
F
F
AGND
M
/S
AGND
A
A
A
A
A
A
AGND
D
C
C
A
O
M
A
A
D
D
D
D
DVDD
AVDD
AD1837
TOP VIEW
(Not to Scale)
NC NO CONNECT
PIN FUNCTION DESCRIPTIONS
Input/
Output
Pin No.
Mnemonic
Description
1, 39
2
3
4
5, 10, 16, 24, 30, 35
6, 8, 12, 14, 25, 27, 31, 33
7, 13, 26, 32
9, 15, 28, 34
11, 19, 29
17
18
20
21
22
23
36
37
38
40, 52
41–44
45
46
47
48
49
50
51
DVDD
CLATCH
CIN
PD
/
RST
AGND
NC
OUTLx
OUTRx
AVDD
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
M
/S
DLRCLK
DBCLK
DGND
DSDATAx
ABCLK
ALRCLK
MCLK
ODVDD
ASDATA
COUT
CCLK
Digital Power Supply. Connect to digital 5 V supply.
Latch Input for Control Data.
Serial Control Input.
Power-Down/Reset.
Analog Ground.
Not Connected.
DACx Left Channel Output.
DACx Right Channel Output.
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor Connection. Recommended 10
m
F/100 nF.
Reference Filter Capacitor Connection. Recommended 10
m
F/100 nF.
ADC Left Channel Negative Input.
ADC Left Channel Positive Input.
ADC Right Channel Negative Input.
ADC Right Channel Positive Input.
ADC
Master
/Slave Select.
DAC LR Clock.
DAC Bit Clock.
Digital Ground.
DACx Input Data (Left and Right Channels).
ADC Bit Clock.
ADC LR Clock.
Master Clock Input.
Digital Output Driver Power Supply.
ADC Serial Data Output.
Output for Control Data.
Control Clock Input for Control Data.
I
I
I
O
O
I
I
I
I
I
I/O
I/O
I
I/O
I/O
I
O
O
I
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